Currently, in the processes of manufacturing integrated circuits, there are strict requirements on the source/drain junction capacitance of the transistor, so an effective method is needed to reduce the source/drain junction capacitance of the transistor so as to limit it within the desired range.
The prior art provides a method of controlling the source/drain junction capacitance of a semiconductor device by performing Halo implantation, which is introduced in the patent application number 200810201780.0. Referring to FIG. 1, the manufactured semiconductor device comprises:    a semiconductor substrate 10;    a gate structure located on the semiconductor substrate 10, the gate structure comprising a gate dielectric layer 11 and a gate 12;    spacers 14 located on both sides of the gate structure;    a source extension region 17, a drain extension region 13 and Halo implantation regions 130 in the semiconductor substrate 10; and    a source region 15 and a drain region 16 in the semiconductor substrate 10.
In the above structure, the Halo implantation regions 130 are distributed symmetrically in the semiconductor substrate 10.
In order to further improve the performance of the CMOS field effect transistor, Aditya Bansal et. al. published an article titled “Asymmetric Halo CMOSFET to Reduce Static Power Dissipation With Improved Performance” in IEEE Transactions on Electron Devices, wherein the technical solution discloses an asymmetric Halo implantation region which is located under the channel region and close to either one of the source region and the drain region. It is found that compared to asymmetric Halo implantation region, the asymmetric Halo implantation region can reduce the static power dissipation of the CMOS field effect transistor and improve the performance thereof.
However, in both of the above-mentioned two technical solutions, the Halo implantation is performed after forming the gate structure and before or after performing lightly-doped ion implantation, so they have such a problem as that the ions for Halo implantation will enter the source/drain regions and cause the junction current and junction capacitance of the transistor to increase because the ions for Halo implantation have a polarity opposite to that of the ions for source/drain implantation, thereby causing the power consumption of the device to increase.